In conventional processing of semiconductor devices, such as fin field-effect transistor (FinFET) devices, nanosheet devices or vertical field-effect transistor (VFET) devices, current middle of line (MOL) contact schemes require selectively removing an intra-gate material (material between gate structures) selective to a gate hard mask material. Typically, this includes removing an oxide selective to a nitride.
Achieving selective etching between two inorganic materials like an oxide and a nitride is very difficult, and at times, may not be possible. The inability to selectively etch intra-gate material with respect to gate hard mask material can cause erosion of gate hard mask material, which can lead to shorts between contacts and gates. In addition, loss of the gate hard mask material can result in gate height loss. One solution is to increase hard mask height, but that forces incoming gate height to be increased, which increases the stresses placed on gate patterning and structural stability.
Creating a robust self-aligned contact (SAC) oxide etch that is selective to a nitride gate cap and gate spacer is very challenging and relies on many factors, such as, for example, incoming SAC cap height, aspect ratio of the contact, and overlap of the nitride cap and spacers. A successful SAC etch requires precise polymer formation on the gate cap. Not enough polymer will prevent sufficient protection, and too much polymer will result in an etch stop. Furthermore, polymer balance can change if contact-to-gate alignment changes or if the space between gates changes. The problem is further complicated by the fact that selectivity between oxides and nitrides is finite, and oxides and nitrides may be etched under similar plasma conditions.
Accordingly, there is a need for improved methods to address the limitations of removing an intra-gate material selective to a gate hard mask material when forming contact structures.